Program counter with ripper adder in VHDL

I would start again, and think about making the design synchronous. Currently, with it being asynchronous, you are likely to run into all sorts of timing problems and it is unlikely to work very well, if at all.

Secondly, you have not written any functions. You have created entities. You cannot use an entity inside a process, you can only instantiate it in parrallel to processes. Communication between processes/entities is done via signals.