Program counter with ripper adder in VHDL

No

What you are doing is turning pc_increment into a clock. What you are also describing is software.

In VHDL, you dont pass values into an entity, and take the results and pass them to something else. You have to remember that all signals run in parrallel. Without a clock, there is no easy way to ensure that event A happens before event B.

First thing - go back and learn about digital logic design. From what you have posted, you are clearly a software programmer with little knowledge of digital design. Learn how digital logic works before trying to write VHDL

Second. Delete all your code and start again with a clock.