Forum Discussion
Altera_Forum
Honored Contributor
12 years agoThe while loop could be used to wait on a signal:
process(clk)
begin
if rising_edge(clk) then
while some_input = 0 loop
--do something
end loop;
end if;
end process;
THis is completly unsuitable for synthesis as it does not map to any real logic circuit. Its not an argument of While vs for - you can also write code that wont synthesis a for loop.