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Altera_Forum
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12 years ago

processes: while loop does not work, for loop does work. Why?

I want to write this code for a basic synchronous counter more efficiently... u_count: process(rst_i, clk_i) -- generated on rising edge variable i: integer :=1; begin if rst_i = '1' ...
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Altera_Forum
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12 years ago

Tricky,

Thanks for the suggestion. I had in fact also tried "variable i : integer range 1 to 16;" and got the same bad result. That means it is not a problem of undefined range in the compiler.

I think you are saying the WHILE is evaluated as if it were logic but in my view it is shorthand for a text expansion prior to any evaluation of logic and consideration of clock edges.

I'm still convinced the compiler is not being faithful to VHDL. One of my VHDL books (old but good) is by Kevin Skahill from Cypress Semi and he has a handy example in chapter 4.5.1. Cypress' compiler obviously handles WHILE back in 1996. It would be nice if Altera wrote an app note on this.