processes: while loop does not work, for loop does work. Why?

To write efficient code for a synchronous counter, just type

c <= c +1;

If you want to write low level code for some reason, e.g. as an exercise, you are restricted to synthesizable VHDL constructs.

You probably have noticed that not all legal VHDL constructs are synthesizable. They can be however used in testbenches.

Because iterations are enrolled to parallel hardware, it's essential that the number of iterations is constant and can be determined at "compile" time. The while statement in your example has a constant number of iterations, but other possible while statements don't. For this reason, synthesis tools don't support it.

For Quartus, the supported VHDL constructs are listed in the online help. The selection is mostly identical to IEEE 1076.6, ieee standard for vhdl register transfer level (rtl) synthesis.

P.S.: Regarding "efficient code". Even if your code is synthesizable, there's a certain risk that it's not recognized as arithmetic operation and thus won't utilize the fast carry chain. In this case, the resulting hardware will be considerably less efficient, slower and consuming more logic cells than that generated by the simple c <= c +1.