Process Wait Statement

The code provided by lizhi0007 should be synthesizable according to IEEE Standard 1076.6 - Standard for VHDL Register Transfer Level (RTL) Synthesis.

There are many rules that must be abided to for a wait statement to be synthesizable. However, it is incorrect to simply state that such statements are not synthesizable.

The most notable rule is that all the wait statements in a process (yes, there can be more than one) must specify the same edge of a single clock for the process to be synthesizable. This technique is used to specify "implict finite state machines".

Here is an example, extracted from IEEE 1076.6, of a process with multiple wait statements that should be synthesizable:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity Mult is
    port(
        clk   : in  std_logic;
        start : in  std_logic;
        done  : out std_logic;
        A, B  : in  unsigned(3 downto 0);
        Y     : out unsigned(7 downto 0)
    );
end Mult;
Architecture ImplicitFSM of Mult is
    signal intY : unsigned(7 downto 0);
begin
    MultProc : process
    begin
        wait until clk = '1';
        if start = '1' then
            done <= '0';
            intY <= (others => '0');
            for i in A'range loop
                wait until clk = '1';
                if A(i) = '1' then
                    intY <= (intY(6 downto 0) & '0') + B;
                else
                    intY <= (intY(6 downto 0) & '0');
                end if;
            end loop;
            done <= '1';
        end if;
    end process;
    Y <= intY;     -- final state Y = A * B
end; 
 

I wonder when Quartus will support that?