Process Wait Statement

--- Quote Start ---

No exactly for my problem!!! Please help me!!!

This code I copy from book, which illustrates about "wait until", i don't know what wrong???

--- Quote End ---

There is nothing wrong with the code but wait statements are non-synthesizable .

i.e. to quote wikipedia...

"A large subset of VHDL cannot be translated into hardware. This subset is known as the non-synthesizable or the simulation-only subset of VHDL and can only be used for prototyping, simulation and debugging."

i.e. as others have already state your code is fine for test-benches and simulation but cannot be turned into logic for an FPGA.

Take a look at this page

http://www.asic-world.com/vhdl/

Maybe it will help clarify some of the difference between RTL code than can be synthesized and behavioral code (like yours) that is OK for test-benches