Process Wait Statement

This is the difference between synthesisable code and compilable behavioural code.

The code you have posted is perfectly legal VHDL and should compile in a simulator fine. You could, for example, use this in a testbench.

However, synthesisable code is a much smaller subset of the VHDL language and includes only code that corresponds exactly to gates and registers.

Your book isn't necessarily giving you code that is synthesisable! Quartus is giving an error because it is trying to synthesise your code.

This site is a good introduction to VHDL:

http://www.doulos.com/knowhow/vhdl_designers_guide/