Honored Contributor
Honored ContributorHi,
the code you provided is'nt synthesizable at all; it seems like you try to synthesize a bevahioural model for simulation. the correct process would include a sensitivity list with asynchronous reset and the clock input like MyStateReg : process (inResetAsync, iClk) is begin if inResetAsync = cnAcivated then elsif rising_edge(iClk) then -- here is your stuff end if; end process; However, I would recommend using the 2 process method as proposed by Gaisler (Gaisler Research) to keep your design readble, servicable and 100% synthesizable. regards, lestard
