process error ... sensitivity list or wait statement?

HI. I am starter in vhdl.

I wrote the source , but it doesn't work...

Quartus said that process statement must contain either sensitivity list or wait statement:mad:.. but I can't understant what it means..

How can i solve this problem?..

If anybody is possible,, show me the right source with below source.

Thanks!

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY ex is

PORT(

c : IN std_logic;

d : IN std_logic_vector(3 downto 0);

x : OUT std_logic_vector(3 downto 0));

end ex;

ARCHITECTURE arc of ex is

BEGIN

PROCESS

BEGIN

FOR i IN 3 downto 0 loop

x(i)<= d(i) XOR c;

END loop;

END PROCESS;

END arc;