New Contributor
Regular ContributorHi,
You will need to try to recompile your design in different seeds to see if it is able to close the timing. May I know if the timing issue will impact your testing?
New ContributorHi,
To reiterate the issue that we’re facing, it is that the timing constraints are not being met when we are synthesising our code using quartus for the purpose of getting the GBS file as output. The error files are attached in one of the previous messages.
We want to know how we can send a lower frequency of clock (user clock having 300 MHz) in the right manner to the avst decimator file so that we don’t get the timing constraints not met error.
We’re referring to the streaming dma afu bbb provided by Intel.
Thank you
