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Altera_Forum
Honored Contributor
17 years agoThanks for the response. I have a few follow up questions. The input and output lines for the data are different, do I use a tri-state buffer to control whether I want to read/write the DQ lines of the RAM (which would be bidirectional). As for the phase shift between the SSRAM clock and the data my main concern is that I am not sending the data in "packets", I am more or less loading it into a shift register, then interrupting its clock, and simply reading it as static levels. Any suggestions on how to create this phase shift of 180 would be appreciated. Thanks.
Andre