Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Problems with verilog state machine

Hi.

My state machine seems to get stuck in one of the states, but if you remove px_gate it begins to work properly. I can not understand this strange behavior.

Code: 


module sync2de(clk,hs,vs,px_in,de,px_out); 
input clk; 
input hs; 
input vs; 
input px_in; 
output px_out; 
output de; 
wire px_gate; 
reg  state=0; 
reg  counter; 
 
 
assign px_out=clk  && px_gate; 
 
always@(state) 
begin 
    case(state) 
        0: begin 
                px_gate=1; 
                de=1; 
            end 
        1: begin 
                de=0; px_gate=1; 
            end  
        2: begin 
                de=0; px_gate=1; 
            end  
        3: begin 
                de=0; px_gate=0; 
            end  
        4: begin 
                de=0; px_gate=0; 
            end  
    endcase 
end  
 
 
always@(negedge clk) 
begin 
    case(state) 
        0:  //wait sync 
            begin 
                if(!vs) 
                    begin 
                        counter=v_blank_lines-1; 
                        state=1; 
                    end 
                else 
                if(!hs) 
                    begin  
                        counter=h_blank_px-1; 
                        state=2; 
                    end 
            end 
        1:  // vs 
            begin 
                 
                if(counter) 
                begin 
                    state=3; 
                end  
                else counter=counter-1; 
            end 
        2: //hs 
            begin 
                 
                if(counter) 
                begin 
                    state=4; 
                end  
                else counter=counter-1; 
            end 
        3: //vs_end 
            begin 
                 
                if(vs) 
                begin     
                    state=0; 
                end 
            end 
        4: //hs_end 
            begin 
                 
                if(hs) 
                begin 
                     
                    state=0; 
                end 
            end  
    endcase 
end 
 
endmodule
Thanks.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Apart from the design being incomplete (missing constants) I don's see a particular problem related to px_gate, because it's not affecting the state machine operation.

    As a more general comment, if the hs and vs input signals are not synchronous to clk or don't keep the setup and hold times related to clk, there's a good chance for the state machine to get stuck at an illegal state. hs and vs need to be synchronized to clk in this case.

    There's also a risk, that the state machine doesn't reset properly, depending on the initial behaviour of clk and input signals. A synchronously released reset according to the suggestions in the Quartus software handbook avoids this problem.

    P.S.: As every gated clock, the output clock can be expected to have glitches. This isn't a problem for the present design, but for succeeding logic.