Problems with verilog state machine

Apart from the design being incomplete (missing constants) I don's see a particular problem related to px_gate, because it's not affecting the state machine operation.

As a more general comment, if the hs and vs input signals are not synchronous to clk or don't keep the setup and hold times related to clk, there's a good chance for the state machine to get stuck at an illegal state. hs and vs need to be synchronized to clk in this case.

There's also a risk, that the state machine doesn't reset properly, depending on the initial behaviour of clk and input signals. A synchronously released reset according to the suggestions in the Quartus software handbook avoids this problem.

P.S.: As every gated clock, the output clock can be expected to have glitches. This isn't a problem for the present design, but for succeeding logic.