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Honored Contributor
Honored Contributorproblems with SERDES
hellow, We have to transmit a pulse to a laser, this pulse is between 0.2 and 1µs. and a duty cycle between 50 and 100ns. This signal we have to 'catch', herefor we will use the high spe...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- You might want to peruse this thread (http://www.alteraforum.com/forum/showthread.php?t=23214&page=4) first. It discusses a similar setup. --- Quote End --- Mathias, did you read that post? Anyway, you can use the generated PLL clock in stead of the CDR-clock in Stratix II (and up) Serdes by setting the lock_to_reference bit. You can feed the photodetector input into the RX-pin of the FPGA and get up to 160 ps resolution. I have no idea how accurate the bit-sampling will be as the input signal is totally asynchronous to the Serdes receiver clock (meta-stability issues?). I suspect you are setting up a LIDAR-like system?
