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You might want to peruse this thread (
http://www.alteraforum.com/forum/showthread.php?t=23214&page=4) first. It discusses a similar setup.
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Mathias, did you read that post?
Anyway, you can use the generated PLL clock in stead of the CDR-clock in Stratix II (and up) Serdes by setting the lock_to_reference bit. You can feed the photodetector input into the RX-pin of the FPGA and get up to 160 ps resolution. I have no idea how accurate the bit-sampling will be as the input signal is totally asynchronous to the Serdes receiver clock (meta-stability issues?).
I suspect you are setting up a LIDAR-like system?
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