Forum Discussion
New ContributorProblems using a Dual access on-chip memory module (QSYS)
So I finally solved the issue...
The problem was that the frame_buffer address immediately changed back after 1 clock cycle. Since the memory has a delay it needs to be kept at their desired value for at least 2 clocks cycles, doing this will result in the readdata value changing in the third clock cycle. I have another post on reddit with a bit more context:
https://www.reddit.com/r/FPGA/comments/y1fkb1/problem_accessing_sdram_from_nios_iie_and_vhdl/
Frequent ContributorHi,
I see that you managed to get the pixel pattern changing on your screen now, so may I know what is the current issue that you have?
Regards,
Kelly
New ContributorSo, the pattern changes because I am setting the first byte of the memory (address 0). See this code snippet:
int main(void) { u8* addr = FRAME_BUFFER_BASE; //Starting point of the video buffer u8 color = 255; *(addr) = 0xFF; *(addr+1) = 0; *(addr+2) = 0; *(addr+3) = 0xFF; while(1){} }
this SHOULD result in pixel 1 = WHITE, pixel 2 = BLACK pixel 3 = BLACK pixel 4 = WHITE. But whenever I try to read from another address in memory, the output does not change. Because it is not responding to the address change (in VHDL). See this signal tap:
The frame_buf_addr changes but readdata field does not change into the next 32 bits. Because it does not increment it just repeats the pattern of the first 4 pixels(32 bits) throughout the whole screen
I want to cycle through the whole memory in VHDL so I can draw graphics like squares/circles.
Regards,
Mart
