Forum Discussion
MartBent
New Contributor
New ContributorProblems using a Dual access on-chip memory module (QSYS)
Hello,
I have a QSYS system using a Nios II/e processor along with some vhdl modules which should be able to display pixels on a LCD display using a VGA controller. I have already managed to get t...
So I finally solved the issue...
The problem was that the frame_buffer address immediately changed back after 1 clock cycle. Since the memory has a delay it needs to be kept at their desired value for at least 2 clocks cycles, doing this will result in the readdata value changing in the third clock cycle. I have another post on reddit with a bit more context:
https://www.reddit.com/r/FPGA/comments/y1fkb1/problem_accessing_sdram_from_nios_iie_and_vhdl/
sstrell
Super Contributor
Super ContributorCan you confirm the Nios is correctly writing data to the frame buffer? If you don't have the correct data in the RAM, then the data you read won't be what you expect.
MartBentThanks for reply, I am able to set the memory using the FRAME_BUFFER_BASE constant in the nios header files. When I set it you can even see the pattern on the screen changing.
