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Altera_Forum's avatar
Altera_Forum
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15 years ago

problem with VHDL

I have been involved in some programming project but suddenly a problem started coming.

in the timing.vhd file from line 114 to 147 i have defined two signals sSTOP and sStop_1 as well as sTEMP. when I simulate these files with timing as a top level entity, the vector waveform file always show a negative sSTOP signal, not only this the initial value of sTEMP is "001" but it takes some random value.

is there a bug in the software?

if not when i try to burn the same project on cyclone III it never shows me the output

kindly help me in this and please rectify if there are some mistakes .

thanq

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Your zip file seems to be corrupted. Just embed your code in your message between code tags.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    sorry there was some error now i have uploaded again

    plz try this one

    begin

    ACC1 :acc port map (

    inp => sCHANNEL(to_integer(sTEMP)),

    rst => sRST,

    clk => sCLK,

    imp => sComp,

    op => sOP

    );

    counter1 : counter port map (

    rst => sRST,

    trigger => sTRIG_in,

    clk => sCLK,

    digit => sDIGIT

    );

    compare1 : compare port map (

    clk => sCLK,

    rst => sRST,

    inp1 => sOP,

    inp2 => sDIGIT,

    output => sComp

    );

    proc1 : proc port map (

    inp_pulse => sComp,

    clk => sCLK,

    rst => sRST,

    op => sOutput

    );

    sSIGNAL <= (others => '0');

    process(rst,clk)

    begin

    if (rst = '1') then

    sTEMP <= "001";

    sStop_1 <= '1';

    -- sOP <= (others => '1');

    elsif (clk'event and clk = '1' and sCOMP = '1') then

    sTEMP <= sTEMP + "001";

    if (sTEMP = "100") then

    sStop_1 <= '0';

    end if;

    end if;

    end process;

    Process (rst, clk)

    begin

    if (rst = '1') then

    sSTOP <= '1';

    elsif (clk' event and clk = '1') then

    if (sCHANNEL(to_integer(sTEMP))=X"00000") then

    sSTOP <= '0';

    end if;

    end if;

    end process;

    --sample1 <= sStop_1;

    --sample <= sSTOP;

    sRST <= rst;

    sCLK <= clk;

    sTrig_in <= trig_in;

    sCHANNEL <= CHANNEL;

    output <= sSTOP and sOutput and sStop_1;

    end behavior;
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    looking at your code, once sStop goes to '0', it stays there until async reset is asserted. Did you mean it to work like this?