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Altera_Forum's avatar
Altera_Forum
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15 years ago

problem with VHDL

I have been involved in some programming project but suddenly a problem started coming. in the timing.vhd file from line 114 to 147 i have defined two signals sSTOP and sStop_1 as well as sTEMP...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Your zip file seems to be corrupted. Just embed your code in your message between code tags.