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Altera_Forum
Honored Contributor
Honored Contributorproblem with VHDL
I have been involved in some programming project but suddenly a problem started coming. in the timing.vhd file from line 114 to 147 i have defined two signals sSTOP and sStop_1 as well as sTEMP...
Altera_ForumHonored Contributor
Honored Contributorlooking at your code, once sStop goes to '0', it stays there until async reset is asserted. Did you mean it to work like this?
