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Honored Contributor

15 years ago

problem with VHDL

I have been involved in some programming project but suddenly a problem started coming. in the timing.vhd file from line 114 to 147 i have defined two signals sSTOP and sStop_1 as well as sTEMP...

timing with single channel.zip6 KB

Altera_Forum

Honored Contributor

15 years ago

looking at your code, once sStop goes to '0', it stays there until async reset is asserted. Did you mean it to work like this?

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problem with VHDL

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