Problem with Partial Word Access from HPS

The problem has been solved.

The byteenable signal behaves differently when accessing from HPS than from System Console.

When accessed from System Console, byteenable is asserted right for the entire transaction.

When accessed from HPS (as observed on DS-5), byteenable is only asserted right for one clock cycle, then changed to 1111.

This caused problem on my FPGA code. My code assumes that the byteenable will not change during the entire transaction.

I revised the FPGA code to latch byteenable signal and the problem is solved.

Thanks everybody for reading this post.