Problem with IP Compiler for PCIe

Hello everyone!

I am new to HDL and have a problem with my work. I have Cyclone IV GX transceiver starter kit and wanted to test "SOPC Builder Design Example" from "IP Compiler for PCI Express User Guide".

I only changed PCI Express lanes to x1 and disabled "Test out witdh".

After finishing generating the SOPC bilder system I want to compile the design, but when the compilation starts the fitter a problem occurs:

Error (176205): Can't place 89 pins with 2.5 V I/O standard because Fitter has only 62 such free pins available for general purpose I/O placement

Error (176204): Can't place pins due to device constraints

Error (171000): Can't fit design in device

Error: Quartus II 32-bit Fitter was unsuccessful. 3 errors, 36 warnings

Now my question, when I look in the Pin Planer there are 40(!) test_in_pcie_compiler_0 pins. I guess they are the problem, but how do I delete them or even not initialize those pins?

ps.: FPGA: EP4CGX15BF14C8

Thanks for answers!

Best regards

RK