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And What if the tSU/tH become negative? Does it mean that something goes wrong?
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it doesn't matter.
Ideally and right "silicon" deep level of a register both are positive by definition. However, the tool then gives the figures from pins perspective of clk and data as this is more relevant to the designer. This results in a shift of window(of setup + hold) relative to clk edge due to different delays inserted on clk path/data path. a positive setup means it is still before edge and a negative hold means its before edge as well i.e. the window has shifted forward. and vice versa
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