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Altera_Forum
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11 years ago

Problem with Data Integrity & Clock between 2 FPGAs

Hi I have a problem with data integriry & clock between 2 FPGAs. A scheme of my design is inserted at the end. My design consists of 2 Cyclone III FPGAs. Each FPGA has several clock domains, eac...
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Altera_Forum
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11 years ago

Thanks Dave

Well, actually I have the .SDC constraint file, but I constrained only clocks & clock uncertainties, not input & output delay constraints (using set_input_delay & set_output_delay).

Since I used Fast Input/Output Registers in my design, The t_co & t_su should be minimal (how much minimal? I don't know how to utilize TimeQuest for this parameter, but according to an_366 I don't think it will be more than 1 ns).

PCB delays should be about 166*0.5=83 ps at most. Summing up all delays I get at most 2 ns delay. Comparing with 10 ns (half of 50 MHz clock period) it is negligible. So I think input & output delay is not required. Am I right? Did I illustrate my point?