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Altera_Forum
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11 years ago

Problem with Data Integrity & Clock between 2 FPGAs

Hi I have a problem with data integriry & clock between 2 FPGAs. A scheme of my design is inserted at the end. My design consists of 2 Cyclone III FPGAs. Each FPGA has several clock domains, eac...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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I hoped that half of clock cycle is sufficient for all delays

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Why hope when you can "design"?

Did you create a TimeQuest .SDC file? If not, its time to learn.

The synthesis tool will make no attempt to meet external timing if you do not provide it the information it needs to understand what the external timing requirements are.

Cheers,

Dave