Problem with ALTGX - rx_dataout drifting

Solved.

The problem was been in testbench:

1. ALTGX transceivers was clocked from ref PLL.

2. Checker logic in testbench was clocked from another PLL (or from generated clock).

3. At simulation time, the phase calculation error occured thah result in incorrect latching of ALTGX_RX output in checker logic.

I solved this problem by clocking all testbench components from one PLL.

In addition, this incorrect behavior also arise at some input frequencies on PLL.