I created a very simple dual edge detector using D flip flops and a few logic gates. I created this using Megafunctions LPM_DFF, LPM_XOR, LPM_INV, and LPM_AND symbols. This project compiles and creates the VHDL and symbol without issue. When I try to use the symbol in a project, I am unable to compile the project and get the following error. Error (10481): VHDL Use Clause error at lpm_dff_0.vhd(28): design library "work" does not contain primary unit "lpm_components" Error (10800): VHDL error at lpm_dff_0.vhd(28): selected name in use clause is not an expanded name Can help with why this rather straight forward application using only basic Quartus components would give this error? Are there some settings in generating the VHDL that are not correct? I have not changed anything and tried reinstalling. Any help would be greatly appreciated.

You need to import the respective Altera libraries. Review the MegaWizard generated code about the correct naming.

Do you mean the standard Quartus setup requires the import of Altera files in order to work? Can you give me some more detail about how this is accomplished?

--- Quote Start --- Do you mean the standard Quartus setup requires the import of Altera files in order to work? Can you give me some more detail about how this is accomplished? --- Quote End --- Its not Quartus, its a requirement of the VHDL language ... -- Altera LPM components library lpm; use lpm.lpm_components.all; Cheers, Dave

I was hoping someone had seen a similar problem so I wouldn't have to get into too great a detail, but here goes. When I received the original error, I found the following lines in the VHDL generated by the Altera Megafunction for LPM_DFF-- -- use the following when compiling in Quartus II --LIBRARY lpm; --USE lpm.lpm_components.all; -- use the following when compiling in third party tools -- -- add lpm_pack.vhd from the Quartus II library LIBRARY work; USE work.lpm_components.all; I commented out the work one and uncommented the LPM one as follows-- -- use the following when compiling in Quartus II LIBRARY lpm; USE lpm.lpm_components.all; -- use the following when compiling in third party tools -- -- add lpm_pack.vhd from the Quartus II library --LIBRARY work; --USE work.lpm_components.all; This led me to this error--- Error (10482): VHDL error at lpm_dff_0.vhd(44): object "lpm_dff" is used but not declared When I commented out the _0 lines and changed them to take off the _0 as in the following VHDL--- -- PROGRAM "Quartus II 32-bit" -- VERSION "Version 12.1 Build 177 11/07/2012 SJ Web Edition" -- CREATED "Thu Jan 17 23:22:14 2013" LIBRARY ieee; USE ieee.std_logic_1164.all; -- use the following when compiling in Quartus II LIBRARY lpm; USE lpm.lpm_components.all; -- use the following when compiling in third party tools -- -- add lpm_pack.vhd from the Quartus II library --LIBRARY work; --USE work.lpm_components.all; --ENTITY lpm_dff_0 IS ENTITY lpm_dff IS PORT ( clock : IN STD_LOGIC; data : IN STD_LOGIC_VECTOR(0 TO 0); q : OUT STD_LOGIC_VECTOR(0 TO 0) ); --END lpm_dff_0; END lpm_dff; --ARCHITECTURE bdf_type OF lpm_dff_0 IS ARCHITECTURE bdf_type OF lpm_dff IS BEGIN -- instantiate LPM macrofunction b2v_inst : lpm_dff GENERIC MAP(LPM_WIDTH => 1) PORT MAP(clock => clock, data => data, q => q); END bdf_type; I got the following error-- Error (10349): VHDL Association List error at lpm_dff_0.vhd(48): formal "LPM_WIDTH" does not exist Since this indicates the key paramter LPM_WIDTH is not there in substantiated VHDL, I sent out this cry for help. What doesn't make sense to me is why Quartus would generate VHDL that is not usuable in Quartus!! Does anyone have any ideas keeping in mind that I am not generating the VHDL in question but it is being generated by Quartus.

Problem using VHDL from a project lower in the heirarchy in an upper level

14 Replies

Altera_Forum
Honored Contributor
13 years ago
You need to import the respective Altera libraries. Review the MegaWizard generated code about the correct naming.
Altera_Forum
Honored Contributor
13 years ago
Do you mean the standard Quartus setup requires the import of Altera files in order to work? Can you give me some more detail about how this is accomplished?
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
Do you mean the standard Quartus setup requires the import of Altera files in order to work? Can you give me some more detail about how this is accomplished?
--- Quote End ---

Its not Quartus, its a requirement of the VHDL language ...

-- Altera LPM components library lpm; use lpm.lpm_components.all;

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
I was hoping someone had seen a similar problem so I wouldn't have to get into too great a detail, but here goes. When I received the original error, I found the following lines in the VHDL generated by the Altera Megafunction for LPM_DFF--

-- use the following when compiling in Quartus II
--LIBRARY lpm;
--USE lpm.lpm_components.all;

-- use the following when compiling in third party tools --
-- add lpm_pack.vhd from the Quartus II library
LIBRARY work;
USE work.lpm_components.all;

I commented out the work one and uncommented the LPM one as follows--

-- use the following when compiling in Quartus II
LIBRARY lpm;
USE lpm.lpm_components.all;

-- use the following when compiling in third party tools --
-- add lpm_pack.vhd from the Quartus II library
--LIBRARY work;
--USE work.lpm_components.all;

This led me to this error---

Error (10482): VHDL error at lpm_dff_0.vhd(44): object "lpm_dff" is used but not declared

When I commented out the _0 lines and changed them to take off the _0 as in the following VHDL---

-- PROGRAM "Quartus II 32-bit"
-- VERSION "Version 12.1 Build 177 11/07/2012 SJ Web Edition"
-- CREATED "Thu Jan 17 23:22:14 2013"

LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- use the following when compiling in Quartus II
LIBRARY lpm;
USE lpm.lpm_components.all;

-- use the following when compiling in third party tools --
-- add lpm_pack.vhd from the Quartus II library
--LIBRARY work;
--USE work.lpm_components.all;

--ENTITY lpm_dff_0 IS
ENTITY lpm_dff IS
PORT
(
clock : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(0 TO 0);
q : OUT STD_LOGIC_VECTOR(0 TO 0)
);
--END lpm_dff_0;
END lpm_dff;

--ARCHITECTURE bdf_type OF lpm_dff_0 IS
ARCHITECTURE bdf_type OF lpm_dff IS
BEGIN

-- instantiate LPM macrofunction

b2v_inst : lpm_dff
GENERIC MAP(LPM_WIDTH => 1)
PORT MAP(clock => clock,
data => data,
q => q);

END bdf_type;

I got the following error--

Error (10349): VHDL Association List error at lpm_dff_0.vhd(48): formal "LPM_WIDTH" does not exist

Since this indicates the key paramter LPM_WIDTH is not there in substantiated VHDL, I sent out this cry for help.

What doesn't make sense to me is why Quartus would generate VHDL that is not usuable in Quartus!!

Does anyone have any ideas keeping in mind that I am not generating the VHDL in question but it is being generated by Quartus.

Altera_Forum

Honored Contributor

13 years ago

Are you sure you have copied the code correctly? According to:

http://www.altera.com/support/examples/vhdl/v_testdff.html

The LPM component is LPM_FF, not LPM_DFF. A search in my 11.1sp1 installation shows the LPM component (C:\software\altera\11.1sp1\quartus\eda\sim_lib\ 220pack.vhd):


component LPM_FF
        generic(LPM_WIDTH : natural;    -- MUST be greater than 0
                LPM_AVALUE : string := "UNUSED";
                LPM_SVALUE : string := "UNUSED";
                LPM_PVALUE : string := "UNUSED";
                LPM_FFTYPE: string := "DFF";
                LPM_TYPE: string := L_FF;
                LPM_HINT : string := "UNUSED");
        port   (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0) := (OTHERS => '1');
                CLOCK : in std_logic;
                ENABLE : in std_logic := '1';
                SLOAD : in std_logic := '0';
                SCLR : in std_logic := '0';
                SSET : in std_logic := '0';
                ALOAD : in std_logic := '0';
                ACLR : in std_logic := '0';
                ASET : in std_logic := '0';
                Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;

The comments in the example code regarding third party tools are incorrect. All tools can use the LPM library. You just need to create the LPM library, or map it to the work library.

For example, in Modelsim

vlib lpm

vmap lpm [pwd]/lpm

vlib work

vmap lpm [pwd]/work

and then compile the components into that library

vcom -work lpm 220pack.vhd

vcom -work lpm 220model.vhd

Modelsim-ASE already has this library configured with the source built into it.

Cheers,

Dave

Altera_Forum
Honored Contributor
13 years ago
Thanks for you quick help. Your answer provided a key clue. I indeed had to use LP_FF. I verified this using the LPM_PACK file that that the Quartus generated VHDL said to add if you used the work declaration. Again thanks for the help.

I still have one remaining problem that you might be able to shed some light on. When I simulate or compile the lower level block everything is find. When I insert this block in a higher level design and try to compile, I get an error saying all my inputs are not driving logic. All I did was connect input and out pins to the symbol, which compiled and simulated without problems. Any advice??
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---

Thanks for you quick help. Your answer provided a key clue. I indeed had to use LP_FF. I verified this using the LPM_PACK file that that the Quartus generated VHDL said to add if you used the work declaration. Again thanks for the help.

--- Quote End ---

You're welcome.

--- Quote Start ---

I still have one remaining problem that you might be able to shed some light on. When I simulate or compile the lower level block everything is find. When I insert this block in a higher level design and try to compile, I get an error saying all my inputs are not driving logic. All I did was connect input and out pins to the symbol, which compiled and simulated without problems. Any advice??
--- Quote End ---

In your top-level design, are you connecting the ports on your component to signals declared in the top-level architecture, or to ports in the top-level architecture?

If you are only connecting to signals, and those signals come from "nowhere", then that would be the source of your problem. In a simulation, you would see those signals as RED in the waveform viewer if they are not being driven by something.

That's just a guess though ... do you have a working simulation with testbench?

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
I am connecting the signal in the low level block to input and output pins. In the top-level architecture I am connecting the inputs and the outputs of the symbol to input and output pins. I am using ModelSim for the lower level module simulation and these lower level pins read as input and output. Any ideas?
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
I am connecting the signal in the low level block to input and output pins. In the top-level architecture I am connecting the inputs and the outputs of the symbol to input and output pins. I am using ModelSim for the lower level module simulation and these lower level pins read as input and output. Any ideas?
--- Quote End ---

Do you have a testbench wrapped around these components that actually drives the signals though?

For example, take a look at modelsim_example.zip in this thread:

http://www.alteraforum.com/forum/showthread.php?t=32386

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
I am just manually setting the inputs and output in modelsim to do the simulation testing.

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Problem using VHDL from a project lower in the heirarchy in an upper level

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