Forum Discussion
Hi,
with the MSEL signals configured for Active Serial at power-up, the FPGA restarts automatically and the JTAG connection is in error. When I cause an error (I put the data from the serial memory to 1) the JTAG link is operational and I can initialize the FPGA with my FirmWare ,.
after a hot reboot I try to access the flash memory with a script I only have 1 and if I look at the oscilloscope the signals generated: the clock is not generated and the CS either .
if I put the MSEL signals to 0 and I power up, the JTAG connection works but in the same way as previously I cannot read the FLASH memory no generated signals.
the connection between the FPGA and the flash memory is direct and I use the pins of the active serial function (AS_DATA, NCS00, DCLK)
thank you
regards