problem of LVDS's clk

Now I am using LVDS technologe on my board , the chip I am using is stratix2's device EP2S180F1020C5N , I have used the row bank (bank 2) as the LVDS transmit and receive diffrential pair pins ,but I don't konw how to design the clk input and clk output , Enhance PLL and Fast PLL , which one should I change ? And what the IO specific of the clk I should change in order to support the high-speed transmission ?