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Your constraints.tcl script is a huge time-saver. It must have taken a few hours to put it together.
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The way I create this script for a new board is;
1. Use the board vendor "golden reference design" and export its project Tcl file.
2. Cut-and-paste the relevant settings into my custom Tcl, and reformat the pin assignments.
3. Manually check the FPGA pins in the schematic and the VCCIO bank assignments (the most time consuming aspect)
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Ok, after reviewing your script and the Pin Planner tool I can see how your script defined the pins (because everything matches). However, I have a follow-on question: how do you distinguish in your script the difference between input and output pins? Specifically, I'm looking at the script for the accel_csN and accel_int pins (as an example):
set pin(accel_csN) {PIN = G5, IOSTD = "3.3-V LVTTL", DRIVE = "MAXIMUM CURRENT", SLEW = 2}
set pin(accel_int) {PIN = M2, IOSTD = "3.3-V LVTTL", DRIVE = "MAXIMUM CURRENT", SLEW = 2}
The Pin Planner shows accel_csN as an output, while accel_int is an input, yet your script appears to define them identically. (The adc_xxx pins show a similar trait, for example.)
How is the direction (input, output, or bidir) actually specified in the script? What did I miss?
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You didn't miss anything. This is probably a copy-and-paste issue. The pin direction is defined by the top-level VHDL file, which in turn is defined by the "intention" in the schematic. An input signal does not need the drive and slew settings, so that is the copy-and-paste error.
The constraints.tcl settings ideally result in Quartus synthesizing the design without any "missing" pin constraints. Delete the drive and slew rate settings on an output that is used in the design (eg., the LEDs), re-synthesize the design, and you'll see the missing constraints messages.
Cheers,
Dave
Honored Contributor
