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Yes, I remember reading something about ensuring the pin assignments are correct.
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Its better to remember now, rather than after your I/O pins stop working, or you smell burning electronics ...
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I didn't realize the designs you posted were explicitly for the nano - thanks much for the consideration and foresight! Having known-good samples is really useful; I'll be reviewing them in the morning. While it's been a very productive day, my mind now is mostly mush, so I'm calling it a day.
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You can synthesize the examples and download them to your board and they'll work fine. You can then start looking at them to figure out how they work. The SDRAM design includes a JTAG-to-Avalon-MM bridge so that you can read and write to the memory from your PC via JTAG. That same interface can be used to access/test your custom VHDL component.
Cheers,
Dave
Honored Contributor
