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Ahhh... Being a newb with the nano, I think I now understand what you're saying: I should be able to talk directly from Quartus II to the nano via the Altera USB_Blaster driver (I think that's the correct one) to download my design, and simply not bother with the controlpanel app. That is, the driver will supply the JTAG interface to program the Cyclone IV, correct?
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Yes, exactly.
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I'm completing the VHDL edits for a new feature right now, so it will be a short time before I can test this.
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Great!
Since you're new to FPGAs, I'll provide a warning; do not download to your board until you confirm that your pin assignments are correct. If you screw it up, and create driver conflicts, then you risk damaging your board. You can also damage the board by connecting it to incompatible voltages, eg., 5V logic.
The example designs I linked to above have a top-level design entity that includes every single defined pin on the DE0-nano schematic. Look at the two designs and compare what I did to the unused pins, eg., in the basic design the SDRAM pins are statically driven to valid values, whereas in the SDRAM design, the pins are connected to an SDRAM controller.
The DE0-nano has a built-in USB-Blaster. If you want to test your VHDL, then you'll want some way to "look" inside the FPGA. You can do that using the USB-Blaster (I can give you links for that too).
Ask questions here on the forum and you'll get plenty of help.
Cheers,
Dave
Honored Contributor
