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Honored Contributor
Honored ContributorProblem in NiosII based design with different instructions and data memories
Hello, I am a beginner in using qsys for systems design. I have made a simple design that contains: - niosII processor ("e" version) - on chip memory for instructions connected to the niosI...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I think that in order to load the software correctly, the memory for instructions needs to be also connected to the data master port. You must also check when generating the bsp that all your linker sections point to the correct memory (i.e. .text to the instruction memory, .bss, .ro and .rw (IIRC) to the data memory). --- Quote End --- Thank you. It works. However, this means to modify, manually, the linker every time I make modification in my design.
