Forum Discussion
Honored Contributorproblem in interfacing
Hi all,
can any one suggest me how to interface altera cyclone 3 fpga starter kit( EP3C25F324 ) and ti daughter card ( SDALTEVK/NOPB ). i have both boards. when i see both schematic diagram then find some of pins iof HSMC not matched together ( like:- HSYNC , ODDEVEN, VFORMAT etc.). so plz suggest how to interface together. it is possible to interface both devices ?? if no then which device configure to SDALTEVK/NOPB.19 Replies
Altera_ForumRefer to your other thread: http://www.alteraforum.com/forum/showthread.php?t=46923 (http://www.alteraforum.com/forum/showthread.php?t=46923)
- Altera_Forum
hello,
thanks for the reply bt i find some problem in pin planner, when i put hsync,vformate,tx_clk in data and clock out location then it don't support and give a error. and i also change voltage level to 1.8 volt bt it don't work and give error. so what i do. - Altera_Forum
I've had a quick look at the schematics - I can't see an issue.
HSYNC_P/N are driven from the SDALTEVK board to FPGA pins G17/G18 - OK VFORMAT_P/N are driven from the SDALTEVK board to FPGA pins T3/R3 - OK. TX1_CLK_P/N need to be driven from the FPGA from pins H17/H18 - OK. Specify all the above IO standards as LVDS and all should be fine. All the above FPGA pins can be use as required by these signals. Cheers, Alex - Altera_Forum
i am getting issue like Error (169079): Pad 143 of non-differential I/O pin 'TX2_SDA' in pin location L17 is too close to pad 140 of differential I/O pin 'tof_n' in pin location M17 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug.
- Altera_Forum
and also give the location for altera_reserved_tms, altera_reserved_tdo, altera_reserved_tdi, altera_reserved_tck . more issue is to understand the right pins for ek signal.
- Altera_Forum
Quartus assumes the single ended signal is going to cause interference on the differential signal because it's too close.
Add an 'io_maximum_toggle_rate "0mhz"' attribute to any non-differential signals in that bank. Do this as follows: In the 'Pin Planner', find the relevant signal - 'TX2_SDA'. In the 'Toggle Rate' column, enter 0 (zero). Do this for any non-differential signal in the same bank as 'tof_n'. If you can't see the 'Toggle Rate' column, right click anywhere in the column headings and select 'Customise Columns...', find 'Toggle Rate' in the 'Available columns:' box and add it to the visible columns. The JTAG signals (TMS, TDO etc.) are reserved pins - you don't need to assign them. I don't understand what you mean by the 'ek' signal. Cheers, Alex - Altera_Forum
i got this error plz resolve it :-
Error (176172): Can't place node "hsync_n" -- node is a differential I/O node it is placed at G18 and fitter location shows E1. - Altera_Forum
if i assigned hsync_n to E1 location, this error comes again. i dont know why this error comes. i compile my design before many times but this error comes today. plz help me to resolve this error.
- Altera_Forum
If, as you say, it worked before you'll have to work out what it is you've changed to break it...
Have you added any other constraints? There are plenty of conflicting constraints you could add that would stop Quartus from being able to use the pin you've selected. Have you accidentally removed the 'IO_MAXIMUM_TOGGLE_RATE "0MHz"' settings? Cheers, Alex - Altera_Forum
i dont know about that, last night i can done my configuration bt some pins like, tx_clk_out n,p, vformate and some more pins location i can change today and when i compile my design i got this error. if i again move back to all pin location then this error never resolve. if you know about that plz tell me.
where i found this setting because i dont know about Quartus 2 software. i am working 1st time in altera's Fpga.
