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Altera_Forum's avatar
Altera_Forum
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11 years ago

problem in interfacing

Hi all, can any one suggest me how to interface altera cyclone 3 fpga starter kit( EP3C25F324 ) and ti daughter card ( SDALTEVK/NOPB ). i have both boards. when i see both schematic diagram the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Quartus assumes the single ended signal is going to cause interference on the differential signal because it's too close.

Add an 'io_maximum_toggle_rate "0mhz"' attribute to any non-differential signals in that bank. Do this as follows:

In the 'Pin Planner', find the relevant signal - 'TX2_SDA'. In the 'Toggle Rate' column, enter 0 (zero). Do this for any non-differential signal in the same bank as 'tof_n'. If you can't see the 'Toggle Rate' column, right click anywhere in the column headings and select 'Customise Columns...', find 'Toggle Rate' in the 'Available columns:' box and add it to the visible columns.

The JTAG signals (TMS, TDO etc.) are reserved pins - you don't need to assign them.

I don't understand what you mean by the 'ek' signal.

Cheers,

Alex