Primitive

So i am currently converting some of our companies work done on Xilinx FPGA to a Altera FPGA. I have been working on it for a few mounth so far with litlle to no problem. But All i really had to do is change a few FIFO and other cores that was xillinx specific. But now i have come acress a Xilinx primitive that i don't know how to change. In Xilinx the Primitive is Call IDDR2. I am trying to find a similar Core but i am not sure witch or where to find it. So i dug up a litlle on this IDDR2 Primitive and here is what i found:

- From what i understand the IDDR2 block is used to acess a ILOGIC2 primitive

Table 2-2: IDDR2 Port Signals

Port Name Function Description

D Input Data input

C0 Input Clock input, optionally invertible

C1 Input Second clock input having 180° phase difference relative to C0,

optionally invertible

CE Input Clock enable

R Input Reset. Software will issue an error if both R and S are connected

S Input Set. Software will issue an error if both R and S are connected

Q0 and Q1 Output Data outputs

I added some pictures that might help understand the primitive.

here is a link to the data sheet of the xilinx primitive where the IDDR2 is explained:

http://www.xilinx.com/support/documentation/user_guides/ug381.pdf

Any help or advice would be great