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Altera_Forum
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12 years ago

Primitive

So i am currently converting some of our companies work done on Xilinx FPGA to a Altera FPGA. I have been working on it for a few mounth so far with litlle to no problem. But All i really had to do...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

For input DDR, use altddr_in. It's not the same, i.e. you only feed it one clock and it automatically hooks up the rising and falling edge. It usually also latches the data on the falling edge before registering it on the rising, so both upper and lower bits are presented to the fabric in parallel on the rising edge of the clock. You might not have the control signals either, but I've never seen that be a problem.