PreSICE Avalon calibration

Hi,

Pls see my comment below.

1. Does this work for PLLs that are not connected to transceivers, or is being connected to a transceiver a requirement for PreSICE?

• It still works on PLL that doesn't connect to transceiver which I presume you are referring to fPLL here.

1. The PLL does not assert lock on an eval board, but does lock when connected to a transceiver. When not connected to a transceiver, the pll_powerdown pin is controlled via a register.

• I am not sure about your design on your board but byright PLL lock has no dependency on the connected transceiver channel.
  • The factor that I can think of that may affect PLL lock are PLL refclk and PLL reset

1. When I complete step 3, writing a one to enable calibration - the register clears on write. Is this supposed to happen?

• Yes, it's auto clear as explained in user guide chapter 7.2. Calibration Registers (page 582)
  • All calibration enable registers are self-cleared after the calibration process is completed.
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf

Thanks.

Regards,

dlim

HI,

Now this is interesting,

My understanding is ATX PLL is meant to connect to transceiver channel only, not for other usage purpose.

• ATX PLL should be connected to transceiver PHY IP like NativePHY IP and also transceiver PHY reset controller
• Sometime we may use ATX PLL to clock protocol IP like Ethernet IP as example but fundamentally it's used to clock the transceiver channel in the protocol IP.
• The ATX PLL loose lock could be due to your design clocking connection is not correct or IP setting is mismatch with your board hardware setup
  • For instance on ATX PLL -> pll_powerdown
    • Resets the PLL when asserted high. Needs to be connected to a dynamically controlled signal (the Transceiver PHY Reset Controller pll_powerdown output if using this Intel FPGA IP).
    • This is the exact design connection as per user guide doc that user need to follow for it to work properly

If your intention is to clock something else like custom design logic in FPGA core then I suggest to use either fPLL or IOPLL

You can refer to below link for general debug guideline on PLL loose lock issue

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/support/devices/pll/pll-loss-of-lock-checklist.pdf

Thanks.

Regards,

dlim

Hi,

There are some timing diagram for transceiver reset operation in chapter 4 of the user guide doc. You can check it out.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf

Thanks.

Regards,

dlim