PreSICE Avalon calibration

HI,

Now this is interesting,

My understanding is ATX PLL is meant to connect to transceiver channel only, not for other usage purpose.

• ATX PLL should be connected to transceiver PHY IP like NativePHY IP and also transceiver PHY reset controller
• Sometime we may use ATX PLL to clock protocol IP like Ethernet IP as example but fundamentally it's used to clock the transceiver channel in the protocol IP.
• The ATX PLL loose lock could be due to your design clocking connection is not correct or IP setting is mismatch with your board hardware setup
  • For instance on ATX PLL -> pll_powerdown
    • Resets the PLL when asserted high. Needs to be connected to a dynamically controlled signal (the Transceiver PHY Reset Controller pll_powerdown output if using this Intel FPGA IP).
    • This is the exact design connection as per user guide doc that user need to follow for it to work properly

If your intention is to clock something else like custom design logic in FPGA core then I suggest to use either fPLL or IOPLL

You can refer to below link for general debug guideline on PLL loose lock issue

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/support/devices/pll/pll-loss-of-lock-checklist.pdf

Thanks.

Regards,

dlim