Forum Discussion
New ContributorPreconfiguration BSDL Editor for Agilex 7 with disabled F-Tiles
On a design with an AGIA040R39A some of the FHT are disabled. We tried to modify the BSDL file using the “Preconfiguration BSDL Editor for Agilex 7 Devices with F-Tiles” as mentioned here: https://docs.altera.com/r/docs/683748/current/agilex-7-jtag-boundary-scan-testing-user-guide/agilex-7-bst-guidelines
This does modify the BSDL file, but the BSDL file it generates (BSR length 3077 bits) doesn't match the boundary scan register length we're detecting in the device (3061 bits).
We suspect this is because the BSDL editor doesn't include the options for disabling FHT12B or FHT13B. Would disabling these parts of the device reduce the BSR length by 16 bits? If so, can the BSDL Editor be updated, or a modified BSDL file be supplied?
2 Replies
Rob_XJTAG_ASAPHaving looked at the BSDL file generated by the Preconfiguration BSDL Editor, it appears that there are other issues with it because for this FPGA it doesn't generate a valid BSDL file in a number of ways (eg syntax errors, missing cells in the boundary scan register description).
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Thank you very much.
