Power supplies don't rise monotonically

Hello,

Looks like the decoupling of your design is not optimized.

Please use PDN to check your decoupling capacitor requirements according to your Ztarget and target running frequency.

link : https://www.intel.com/content/www/us/en/support/programmable/support-resources/signal-power-integrity/power-distribution-network.html

regards,

Farabi

Hello,

Just want to know if this setup can make the FPGA successfully configured and enter user mode?

regards,

Farabi

Hello Farabi

Thank you for replying.

If this non-monotonicity, can intel guarantee that the FPGA work correctly?

If not, what kind of defects can be expected? (ex; I/O pins output incorrectly, possible corruption ect)

Best regards,

Inoue

Hi,
i'd refer to datasheets. ACEX datasheet e.g. specifies "Maximum VCC rise time is 100 ms, and VCC must rise monotonically" for VCCINT and VCCIO.

In other words, the device is not guaranteed to work correctly if you violate this condition. I won't expect damage, but configuration might fail.

As the shown VCCINT and VCCIO waveforms are nearly montonical, I won't expect failure. But it's obviously bad 5V regulator design that should be fixed.

Out of curiosity, are you newly designing with 20 years old ACEX1K and Cyclone or just servicing old instruments?

Regards
Frank

Hi,

As the query has been answered by members, I am setting the ticket to closure. However, it will be open for communication for community members.

Regards