Power on Reset & state machines

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I tried "pre-setting" this port, in vhdl: foo: std_logic := '1', & it still didnt fix it. shouldnt it have?

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All internal registers (registers not in I/O cells) power up low and cannot be made to power up high. Synthesis might make a register appear to initialize high by inverting the register input and output. I don't know whether synthesis should do that in your case. There are synthesis warnings (might be Info messages) about power-up don't care. They probably relate to this situation. See whether you have warnings about that.