Altera_ForumHonored Contributor18 years agoPower on Reset & state machines Hi, I am using MAX II cplds & have a couple of questions. Can anyone explain to me what state a state machine goes into after Power-Up? if My State_type definition is this: type STATE_TYPE is (A,B...Show More
Recent DiscussionsLooking for the Document ID 854068SolvedAbout floating voltage of the Agilex 3 power on resetSuggestion of carry chain type TDC of Cyclone 10 GX FPGA chipsIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAImplementation of lower data rate.