Power and ground pin decoupling capacitors

Question

Hello everybody,

In the Max II CPLD manual required Power and ground pin decoupling capacitors requirements are stated as follows:

Board Decoupling Guidelines:

Decoupling requirements are based on the amount of logic used in the device and the output switching requirements. As the number of I/O pins and the capacitive load on the pins increase, more decoupling capacitance is required. As many as possible 0.1-mf power-supply decoupling capacitors should be connected to the VCC and GND pins or the VCC and GND planes.

This seems very big, around here we generally use 100 nF on uC pins.

Opinions ?

Thanks,

Eric

altera_forum · Answer

I don't have the document here. Probably this is a typo.

Usually you may need a single big capacitor in the 100uF range to decouple power supply in the middle-low frequency range, near the supply source. The capacitors located near device supply pins are 100nF or 10nF and these are for high decoupling frequencies.

Generally speaking, if no further information is given in a component datasheet I use this rule of thumb: a 100nF and a 10nF for each supply pin.

altera_forum · Answer

Super, thanks a bunch Cris72, I really appreciate your answer.  Cheers, Eric

altera_forum · Answer

Hello,

I dont know if this the right place to this quetion, but some one know how obtain the capacitance of instances in a netlist file from Quartus II tool.

I need to use the netlist file from Quartus tool, in the Nanosim tool from Synopsys, because there isn't any Altera tool to obtain the capacitance of a instance (resistor, transistor, capacitor, etc) of a FPGA design.

Thank you for help.

altera_forum · Answer

typically IBIS or HSPICE models are used, but i don't know if Nanosim supports them

altera_forum · Answer

So, did you say that I can use the IBIS or HSPICE to obtain the capacitance from a Quartus netlist, did you? Because the Quartus netlist is a .vo file so I think they don't support.

Do you know if I can set the Quartus to give me another kind of netlist file, like *.sp or *.spi file? These kind of files are supported by Nanosim tool.

Thanks so much.

Forum Discussion

Power and ground pin decoupling capacitors

8 Replies

Recent Discussions

Arria 10 GX RX max intra-differential pair skew

MAX10 Bitstreams Authentication

Cyclone 10 GX development board collaterals

Agilex 7 FPGA Availability on Cloud Platforms (AWS, Azure, GCP)?

AGRW027R28A2I2V Thermal Model