Potential Documentation Error in ES-1057 Errata Doc: "HPS EMAC" Issue Listed for Arria 10 GX/GT

Hello ALTERA FPGA Community / Support Team,

I have identified an apparent inconsistency in the official device errata documentation and would like to seek clarification.

On Jan 5, 2026, a new issue titled "HPS EMAC RX Interface in Unresponsive State" was added to the document ES-1057 "Arria 10 GX/GT Device Errata and Design Recommendations" (accessible via the Altera documentation portal).

Upon reviewing the issue's description, it explicitly details a problem with the Ethernet Media Access Controller (EMAC) block within the Hard Processor System (HPS). The described workaround also involves using software timestamping or reducing the line rate for the HPS EMAC.

However, to my knowledge, the standard Arria 10 GX and GT device families do not integrate a Hard Processor System (HPS). The HPS is a feature found exclusively in the Arria 10 SX and SE device variants.

Therefore, there seems to be a documentation mismatch:

Errata Title/Scope: Arria 10 GX/GT Device Errata and Design Recommendations

Actual Content: Describes an issue specific to the HPS, which is not present in GX/GT devices.

My Question:
Is this entry, "HPS EMAC RX Interface in Unresponsive State," indeed applicable to the GX/GT families? If so, could you please clarify how an HPS-related issue pertains to devices that lack this subsystem?

Thank you for your time and for helping to maintain accurate technical documentation.

Best regards,
Onur