Post synthesis timing analysis using TimeQuest Timing Analyzer

Dear all,

(what the plan?)

I am planning to use DE0 Nano FPGA board for checking a simple example of a counter. Before putting the design into the board, I would like to verify the design (after synthesis, place and route etc) for timing constraints and make sure that my delay constraints are met and the design would work perfectly for the 50MHz clock (of DE0 Nano)

(what is done so far?)

I have tried various clock frequencies in the TimeQuest Timing analyzer and found out that the design is working with a 'minimum pulsewidth slack' of '0ns' when the clock frequency is around 250MHz. If I increase it further, the slack would become negative. From that I assume that, my design will work at a max clock freq of 250 MHz. (attachment 2 is the circuit I have used for this analysis)

(doubts)

1. What are the constraints (other than the clock freq), one should check to make sure that the design will work once it is put in the FPGA ?

2. Should I check setup violation, hold violation etc? If yes, how do I specify the inputs to check them?

3. Are there any constraints like clock to q, clock to pad etc. If yes, where should I specify them and how can I include those while doing synthesis, place & route etc ?

4. Is there any other method to give timing constraints to the design other than through the .sdc file (attachment1 the sample .sdc file generated by the TimeQuest Analyzer) ?

Thanks a lot