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Altera_Forum's avatar
Altera_Forum
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11 years ago

Post synthesis timing analysis using TimeQuest Timing Analyzer

Dear all, (what the plan?) I am planning to use DE0 Nano FPGA board for checking a simple example of a counter. Before putting the design into the board, I would like to verify the design...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi,

1) You will have to check for all violations. Setup, hold etc to make sure design will work on FPGA.

2)Yes you need to check the violations. After you compile your code, under the table of contents you can see the TimeQuest timing analyzer. In case if there are any violations it will be highlighted in red and show you specifically what violations when you expand it.

3 & 4) You need to specify all the constraints in the sdc file. I think this is the only way to do it.

Thanks,