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Altera_Forum
Honored Contributor
Honored ContributorPost synthesis timing analysis using TimeQuest Timing Analyzer
Dear all, (what the plan?) I am planning to use DE0 Nano FPGA board for checking a simple example of a counter. Before putting the design into the board, I would like to verify the design...
Altera_ForumHonored Contributor
Honored ContributorSet period to 20ns into sdc clock
Add false_path from * to led to no constraints output (with led there are no timing to respect) You can compensate clock with a PLL if timing is no meet (check why with timequest)
