Possibility to avoid configuration power requirements for single-supply MAX10 by using nconfig

Hi taka7,

You refer to Intel® MAX® 10 Power Management User Guide for more details on your questions.

In response to your question:

(Question 1) Can the power rise time be completely ignored by the reset IC driving nCONFIG low until the power supply voltage reaches a certain value?

<ANS> No, the power rise time cannot be completely ignored, even if nCONFIG is held low by a reset IC. According to the MAX 10 Power Management User Guide, the Power-On Reset (POR) circuit monitors the power rails (VCC_ONE, VCCA, and VCCIO for banks 1B and and ensures they reach the recommended operating voltage within the specified ramp time. If the ramp time (tRAMP) is not met, the FPGA may not exit the reset state properly, and configuration could fail​

However, if nCONFIG is held low, the FPGA will not start configuration until it is released. This means that the timing requirement for configuration start can be controlled, but it does not override the need for power rails to ramp up properly to meet the device specifications.

(Question 2) If question 1 is possible, what is the appropriate threshold voltage for the reset IC?

<ANS> If you are using a reset IC to hold nCONFIG low, the threshold voltage should be selected to ensure that all monitored power supplies (VCC_ONE, VCCA, and VCCIO of banks 1B and have reached a stable level above the POR trip voltage before releasing nCONFIG.

Based on the recommended voltage range for a 3.3V single-supply MAX 10 device (3.135V to 3.465V), a good reset IC threshold would be around 3.0V to 3.1V. This ensures that the supply is within the acceptable range before the FPGA attempts to configure. Additionally, you should verify the POR delay (typically 2.5 ms) to ensure stability before releasing nCONFIG​.

Regards,

Fakhrul