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Altera_Forum
Honored Contributor
13 years agoAttached is my compilation results from the source code with current FPGA.
Is there any flow or tips for me to do for porting this code to a new FPGA? Thanks and RegardsAttached is my compilation results from the source code with current FPGA.
Is there any flow or tips for me to do for porting this code to a new FPGA? Thanks and Regards